Semiconductor device technologies continue to evolve, providing higher chip density and operating frequencies. Fin-type field-effect transistors (FinFETs) are one type of transistor technology that is currently used to help provide desired device scaling while maintaining appropriate power consumption budgets.
A fin-type field effect transistor is a transistor that is formed with a fin of material. A fin is a relatively narrow width and relatively tall height structure that protrudes from the top surface of a semiconductor layer. The fin width is intentionally kept small to limit the short channel effect.
In a conventional FinFET, a gate conductor is positioned on the top surface of the semiconductor layer and over a portion of the fin. The gate conductor runs parallel to the top of the semiconductor layer and is perpendicular to the fin length such that the gate conductor intersects a portion of the fin. An insulator (e.g., gate oxide) separates the gate conductor from the fin. Further, the region of the fin that is positioned below the gate conductor defines a semiconductor channel region. The FinFET structure can include multiple fins, in which case the gate conductor would wrap around, as well as fill in, the space between these fins.
The fins extend across the active area of the semiconductor layer into where the raised source/drain regions are to be formed. A selective epitaxial growth/deposition process is used to form the raised source/drain regions. The raised source/drain regions typically comprise epitaxially grown silicon (Si) or silicon germanium (SiGe), for example.
More particularly, epitaxially growing Si and SiGe facets may not form a rectangular profile on a silicon substrate having a (001) crystallographic orientation with a notch aligned in a <110> direction. Facets of the fin structure may exhibit a diamond shaped profile, which often occurs in conventional processing. This makes it difficult for source/drain extension formations since diamond shaped epitaxy is difficult to drive the dopants in the channel for a good overlap.
One approach to form raised source/drain regions is disclosed in U.S. Pat. No. 8,310,013, which uses a damascene process to form the facets of the fin structure, i.e., the raised source/drain regions of the FinFET. The damascene process can be utilized to form unique and/or arbitrary profiles of the fin structure including the facets. The damascene process can utilize a capping layer that is patterned to define a desired facet profile. The capping layer can provide improved profile control. For example, the facets may be formed having a rectangular profile. Nonetheless, there is still a need for other approaches to form raised source/drain regions for a FinFET.